Compatible embedded DRAM process for MIM capacitor

ABSTRACT

A method and system for fabricating a capacitor utilized in a semiconductor device. A salicide gate is designated for use with the semiconductor device. A self-aligned contact (SAC) may also be configured for use with the semiconductor device. The salicide gate and the self-aligned contact are generally in a memory cell area of the semiconductor device to thereby permit the efficient shrinkage of memory cell size without an additional mask or weakening of associated circuit performance. Combining, the self-aligned contact and the salicide gate in the same memory cell area can effectively reduce gate resistance.

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor device andmanufacturing method thereof. More specifically, the present inventionrelates to a semiconductor device having a capacitor and a contact plugin a DRAM (Dynamic Random Access Memory) or the like, and to amanufacturing method thereof. The present invention also relates to MIMcapacitor fabrication methods and systems.

BACKGROUND OF THE INVENTION

[0002] A semiconductor memory, such as a DRAM, mainly consists of atransistor and a capacitor. Therefore, improvement in the efficiency ofthese two structures tends to be the direction in which technology isdeveloping. DRAM is a volatile memory, and the way to store digitalsignals is decided by charge or discharge of the capacitor in the DRAM.When the power applied on the DRAM is turned off, the data stored in thememory cell completely disappears. A typical DRAM cell usually includesat least one field effect transistor (FET) and one capacitor. Thecapacitor is used to store the signals in the cell of DRAM. If morecharges can be stored in the capacitor, the capacitor has lessinterference when the amplifier senses the data. In recent years, thememory cell of a DRAM has been miniaturized more and more fromgeneration to generation. Even if the memory cell is minimized, aspecific charge is essentially stored in the storage capacitor of thecell to store the information.

[0003] When the semiconductor enters the deep sub-micron process, thesize of the device becomes smaller. For the conventional DRAM structure,this means that the space used by the capacitor becomes smaller. Sincecomputer software is gradually becoming huge, even more memory capacityis required. In the case where it is necessary to have a smaller sizewith an increased capacity, the conventional method of fabricating theDRAM capacitor needs to change in order to fulfill the requirements ofthe trend.

[0004] There are two approaches at present for reducing the size of thecapacitor while increasing its memory capacity. One way is to select ahigh-dielectric material, and the other is to increase the surface areaof the capacitor.

[0005] There are two main types of capacitor that increase capacitorarea. These are the deep trench-type and the stacked-type, where diggingout a trench and filling the trench with a conductive layer, acapacitive dielectric layer and a conductive layer in sequence for thecapacitor form the deep trench-type capacitor.

[0006] When a dielectric material with a relatively high dielectricconstant is used in a stacked capacitor, the materials for manufacturingthe upper and the bottom electrodes need to be gradually replaced inorder to enhance the performance of the capacitor. A structure known asa metal-insulator-metal (MIM) structure possesses a low-interfacialreaction specificity to enhance the performance of the capacitor.Therefore, it has become an important topic of research for thesemiconductor capacitor in the future.

[0007] Cell areas are reduced, as a semiconductor device needsultra-high integrity. Thus, many studies for increasing the capacitanceof a capacitor are being developed. There are various ways of increasingthe capacitance such as forming a stacked or trench typedthree-dimensional structure, whereby a surface area of a dielectriclayer is increased.

[0008] In order to constitute a cell area in a DRAM fabrication,transistors and the like are formed on a semiconductor substrate,storage and plate electrodes of polycrystalline silicon and a dielectriclayer are formed wherein the dielectric layer lies between theelectrodes, and metal wires are formed to connect the devices oneanother.

[0009] The obtainable capacitance of the storage capacitor tends todecrease dependent upon the level of the miniaturization of the storagecell. On the other hand, the necessary capacitance of the capacitor isalmost constant when the storing voltage to be applied across thecapacitor is fixed. Therefore, it is necessary for the capacitor tocompensate the capacitance decrease due to the miniaturization by, forexample, increasing the surface area of the capacitor. This surface areaincrease has been popularly realized by increasing the thickness of thelower electrode (or, storage electrode) of the capacitor. A typicalcapacitor utilized in DRAM fabrication is the Metal Insulator Metal(MIM) capacitor, which is usually located in the memory region of DRAMand embedded DRAM to increase the capacitance of the capacitor.

[0010] In the conventional method of fabricating a semiconductor device,a polysilicon material is usually to be taken for the electrodes of thecapacitors. In this case, the higher the temperature is used in theprocess of annealing on the dielectric thin film, the lesser the defectexists in the dielectric thin film.

[0011] In conventional embedded DRAM fabrication processes, aCo-salicide gate is generally utilized in association with logiccircuits. The term “Salicide” generally refers to “self-alignedsilicide” and is well known in the art of DRAM semiconductorfabrication. It is difficult to apply Co-salicide gate for use in memorycells. The root cause of this difficulty lies in the fact that in orderto utilize a Co-salicide gate efficiently, it is necessary to possessenough of a gate to contact extension for window process, which resultedin the ability of the cell size to shrink efficiently. Although SAC(self-aligned contact) is generally better to utilize for gateresistance performance and is more compatible with logical processes,the SAC process is difficult to use in reducing cell size and continuesto present drawbacks.

[0012] Thus, the present inventor has concluded that a need exists for anew process, which combines the salicide gate, and SAC process in thememory cell area without the need for extra mask and trading-off circuitperformance.

BRIEF SUMMARY OF THE INVENTION

[0013] The following summary of the invention is provided to facilitatean understanding of some of the innovative features unique to thepresent invention, and is not intended to be a full description. A fullappreciation of the various aspects of the invention can be gained bytaking the entire specification, claims, drawings, and abstract as awhole.

[0014] It is therefore one aspect of the present invention to provide animproved semiconductor fabrication method and system.

[0015] It is another aspect of the present invention to provide a methodand system for fabricating a MIM capacitor.

[0016] It is yet another aspect of the present invention to provide amethod and system for fabricating a MIM capacitor utilized in aDRAM-based semiconductor device.

[0017] It is yet another aspect of the present invention to combine asalicide gate and SAC (self-aligned contact) techniques in a memory cellwithout requiring an additional photo mask and trade-offs in circuitperformance thereof.

[0018] The above and other aspects of the present invention are achievedas is now described. A method and system for fabricating a capacitorutilized in a semiconductor device. A salicide gate is designated foruse with the semiconductor device. A self-aligned contact (SAC) may alsobe configured for use with the semiconductor device. The salicide gateand the self-aligned contact are generally in a memory cell area of thesemiconductor device to thereby permit the efficient shrinkage of memorycell size without an additional mask or weakening of associated circuitperformance. Combining, the self-aligned contact and the salicide gatein the same memory cell area can effectively reduce gate resistance.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying figures, in which like reference numerals referto identical or functionally-similar elements throughout the separateviews and which are incorporated in and form part of the specification,further illustrate the present invention and, together with the detaileddescription of the invention, serve to explain the principles of thepresent invention.

[0020]FIG. 1 illustrates a first step of a semiconductor fabricationprocess, in accordance with a preferred embodiment of the presentinvention;

[0021]FIG. 2 illustrates a second step of a semiconductor fabricationprocess, in accordance with a preferred embodiment of the presentinvention;

[0022]FIG. 3 depicts a third step of a semiconductor fabricationprocess, in accordance with a preferred embodiment of the presentinvention;

[0023]FIG. 4 illustrates a fourth step of a semiconductor fabricationprocess, in accordance with a preferred embodiment of the presentinvention;

[0024]FIG. 5 depicts a fifth step of a semiconductor fabricationprocess, in accordance with a preferred embodiment of the presentinvention;

[0025]FIG. 6 illustrates a sixth step of a semiconductor fabricationprocess, in accordance with a preferred embodiment of the presentinvention

[0026]FIG. 7 depicts a seventh step of a semiconductor fabricationprocess, in accordance with a preferred embodiment of the presentinvention;

[0027]FIG. 8 illustrates an eighth step of a semiconductor fabricationprocess, in accordance with a preferred embodiment of the presentinvention;

[0028]FIG. 9 depicts a ninth step of a semiconductor fabricationprocess, in accordance with a preferred embodiment of the presentinvention;

[0029]FIG. 10 illustrates a tenth step of a semiconductor fabricationprocess, in accordance with a preferred embodiment of the presentinvention;

[0030]FIG. 11 depicts an eleventh step of a semiconductor fabricationprocess, in accordance with a preferred embodiment of the presentinvention;

[0031]FIG. 12 illustrates a twelfth step of a semiconductor fabricationprocess, in accordance with a preferred embodiment of the presentinvention;

[0032]FIG. 13 depicts a thirteenth step of a semiconductor fabricationprocess, in accordance with a preferred embodiment of the presentinvention;

[0033]FIG. 14 illustrates a fourteenth step of a semiconductorfabrication process, in accordance with a preferred embodiment of thepresent invention;

[0034]FIG. 15 depicts a fifteenth step of a semiconductor fabricationprocess, in accordance with a preferred embodiment of the presentinvention;

[0035]FIG. 16 illustrates a flow chart of operations illustratingoperational steps that may be followed to implement a preferredembodiment of the present invention; and

[0036]FIG. 17 depicts a flow of operations illustrating continuedoperational steps that may be followed to implement a preferredembodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0037] The particular values and configurations discussed in thesenon-limiting examples can be varied and are cited merely to illustrateembodiments of the present invention and are not intended to limit thescope of the invention.

[0038] The present invention discloses a method and system fabricating aMIM capacitor utilized in a DRAM-based semiconductor device. A salicidegate is designated for use with the semiconductor device. A self-alignedcontact (SAC) may also be configured for use with the semiconductordevice. The salicide gate and the self-aligned contact are generally ina memory cell area of the semiconductor device to thereby permit theefficient shrinkage of memory cell size without an additional mask orweakening of associated circuit performance. Combining, the self-alignedcontact and the salicide gate in the same memory cell area caneffectively reduce gate resistance. (Note that Self-aligned contacts(SACs) can be utilized in many semiconductor technologies, such asDRAMs, SRAMs, and Flash memory.

[0039]FIG. 1 illustrates a first step 11 of a semiconductor fabricationprocess, in accordance with a preferred embodiment of the presentinvention. First step 11 indicates a poly deposition layer 14 locatedabove STI 16 and 18. A TEOS deposition layer 12 is situated above polydeposition layer 14. Finally, an SiN deposition layer 10 is situatedabove TEOS deposition layer 12. Note that the acronym “TEOS,” asutilized herein, refers to “Tetraethoxysilane.” For brevity, however,the term TEOS will be utilized primarily herein. Thus, first step 11 ofFIG. 1 indicates the formation of a gate oxide. Thus, as indicated infirst step 11, DRAM poly gate patterning may be performed utilizing ahard mask. Note that in FIGS. 1 to 15 herein, analogous parts areindicated by identical reference numerals. Thus, FIGS. 1 to 15 togetherrepresent a semiconductor fabrication process that may be implemented inaccordance with a preferred or alternative embodiments of the presentinvention.

[0040]FIG. 2 illustrates a second step 13 of the semiconductorfabrication process disclosed herein, in accordance with a preferredembodiment of the present invention. In second step 13, a poly gate isdefined (i.e., a DRAM gate is defined). Additionally, a cell LDD implantstep is performed. Note that the acronym LDD, which is utilized herein,refers to the term “Lightly Doped.” The term “LDD” is well known in thesemiconductor fabrication arts.

[0041]FIG. 3 depicts a third step 15 of a of the semiconductorfabrication process disclosed herein, in accordance with a preferredembodiment of the present invention. In third step 15 of FIG. 3, severalelements are identified. For example, BPTEOS 40 is indicated in FIG. 3,along with TEOS, poly plugs 34, 36, 38, and SiN 42. Third step 15illustrates a plug implant and poly-plug formation. A TEOS layer, SiN,and BPTEOS layers are thus deposited, and an IPO-1 planarizationoperation is performed. Note that as utilized herein, the acronymBPTEOS, which is well known in the art, refers to “Boro Phospho TetraEtyle Ortho Silicate.” Also, the acronym IPO refers generally to aninter-poly oxide (IPO) layer.

[0042]FIG. 4 illustrates a fourth step 17 of the semiconductorfabrication process disclosed herein, in accordance with a preferredembodiment of the present invention. Fourth step 17 indicates that ananisotropic (oxide+SiN) etch back is performed to stop on a poly gate byutilizing a high selectivity between the poly layer and the oxide andSiN. Additionally, in FIG. 4, an un-doped poly layer 80 is illustrated,along with a doped poly layer 82. The operation illustrated in FIG. 4thus involves an oxide/SiN etch back step.

[0043]FIG. 5 depicts a fifth step 19 of the semiconductor fabricationprocess disclosed herein, in accordance with a preferred embodiment ofthe present invention. As indicated in FIG. 5, the poly gate (i.e.,logic gate) is defined. A resist layer 70 is also indicated in FIG. 5.FIG. 6 illustrates a sixth step 21 of a semiconductor fabricationprocess, in accordance with a preferred embodiment of the presentinvention. As indicated in FIG. 6, the SiON layer is removed, andthereafter, as depicted FIG. 7, LDD implant 50 layer is deposited. FIG.7 thus depicts a seventh step 23 of the semiconductor fabricationprocess disclosed herein, in accordance with a preferred embodiment ofthe present invention.

[0044]FIG. 8 illustrates an eighth step 25 of the semiconductorfabrication process disclosed herein, in accordance with a preferredembodiment of the present invention. As indicated in FIG. 8, a spacerdeposition comprising the following fabrication sequence takes place:TEOS/SiN/TEOS. FIG. 9 depicts a ninth step 27 of the semiconductorfabrication process disclosed herein, in accordance with a preferredembodiment of the present invention. As illustrated in FIG. 9, a spacerTEOS dry etch is performed, with a stop on SiN. Thereafter, as depictedin FIG. 10, a tenth step 29 of the semiconductor fabrication processdisclosed herein, in accordance with a preferred embodiment of thepresent invention, can be performed. In this tenth step 29, a photo maskcan be utilized to open the DRAM array, and a wet dip may be utilized toremove the space TEOS.

[0045]FIG. 11 depicts an eleventh step 31 of the semiconductorfabrication process disclosed herein, in accordance with a preferredembodiment of the present invention. According to the eleventh step 31,a spacer SiN dry etch is performed with a stop on TEOS. A wet dip canthen be performed to remove the space TEOS. Next, as illustrated in FIG.12, a twelfth step 33 of the semiconductor fabrication process can beperformed, in accordance with a preferred embodiment of the presentinvention. As illustrated in FIG. 12, an S/D implant can be performed.The DRAM can also operate during an N+ S/D implant.

[0046]FIG. 13 depicts a thirteenth step 35 of the semiconductorfabrication process disclosed herein, in accordance with a preferredembodiment of the present invention. As indicated in FIG. 13, an RPOphoto and etch step can be performed, resulting in Co-Salicideformation. Co-Salicide 90 is illustrated in FIG. 13. Additionally, a SiNspacer 92 is depicted.

[0047]FIG. 14 illustrates a fourteenth step 37 of the semiconductorfabrication process disclosed herein, in accordance with a preferredembodiment of the present invention. As indicated in FIG. 14, a SiONdeposition step can be performed, along with an ILD deposition and flowoperation.

[0048] Finally, FIG. 15 depicts a fifteenth step 39 of the semiconductorfabrication process disclosed herein, in accordance with a preferredembodiment of the present invention. FIG. 15 depicts a W-plug formationand an M1 (i.e., metal one layer) photo and etch. An MIM capacitor maythus be formed between a metal one layer and a metal two layer for usein standard logic operations.

[0049]FIG. 16 illustrates a flow chart 100 of operations illustratingoperational steps that may be followed to implement a preferredembodiment of the present invention. As described at block 102, a DRAMpoly gate patterning operation may be performed with a hard mask,followed by a cell LDD implant. Thereafter, as illustrated at block 104,TEOS, Sin, and BPTEOS deposition steps may be implemented, followed byan IPO-1 planarization step. Then, as illustrated at block 106, SACpatterning and poly plug formation takes place. An example of thisoperation is illustrated specifically in FIG. 3 herein. As indicatednext at block 108, an anisotropic (oxide and SiN) etch back is performedwith a stop on the poly gate. This operation may be performed utilizinghigh selectivity between the poly gate and the oxide/SiN etch. Anexample of the oxide/SiN etch is illustrated in FIG. 4 herein. Next, asdescribed at block 110, the logic poly gate is generally defined, alongwith the performance of an LDD implant followed by spacer deposition. Anexample of the logic poly gate defining step is illustrated in FIG. 5herein.

[0050]FIG. 17 depicts a flow of operations 101 illustrating continuedoperational steps that may be followed to implement a preferredembodiment of the present invention. Note that the operations depictedin FIG. 17 represent continued operational steps that are describedherein with reference to FIG. 16. Thus, the operation illustrated atblock 112 of FIG. 17 can be processed immediately following theoperation depicted at block 110. As indicated at block 112, a spacerTEOS dry etch may be performed with a stop on a SiN layer (e.g., seeFIG. 9), and followed thereafter by an extra photo mask to open the DRAMarray. A wet dip can be utilized to remove the spacer TEOS (e.g., seeFIG. 10). After a resist stripper operation is performed, as illustratedat block 114, a SiN dry etch with a stop on TEOS can be processed. A wetdip may then be utilized to remove the space TEOS (e.g., see FIG. 11).Then, as illustrated at block 116, an RPO is defined and Co-Salicideformation takes place (e.g., see FIG. 13). Finally, as illustrated atblock 118 standard logical processes may occur using an MIM capacitorformed between a metal one and metal two layer, as a result of theprocessing of the semiconductor fabrication steps described herein.

[0051] Based on the foregoing, it can be appreciated that a number ofadvantages can be obtained by implementing the fabrication method andsystem described herein. For example, the use of a DRAM poly gate with aCo-Salicide can effectively reduce gate resistance. Additionally, anextra metal layer is not required for word-line strapping designs. Aconventional DRAM process requires one or more extra photo/etch steps toopen a SiN/TEOS hard mask above a DRAM level six gate to avoidcontacting an associated gate opening. Utilizing the method and systemdescribed herein, however, can reduce mask layers and associatedprocessing costs. Perhaps most important, by implementing the method andsystem described herein for semiconductor fabrication, an SAC(self-aligned contact) can still be utilized, while effectively enablingthe shrinkage of memory cell sizes. Finally, the method and systemdescribed herein permits a logic gate oxide to be utilized, along withan un-doped poly layer; therefore, the method and system describedherein can be easily combined with logical processes. The inventiondescribed herein thus generally illustrates a new logic compatibleembedded DRAM fabrication process for MIM capacitor devices.

[0052] The embodiments and examples set forth herein are presented tobest explain the present invention and its practical application and tothereby enable those skilled in the art to make and utilize theinvention. Those skilled in the art, however, will recognize that theforegoing description and examples have been presented for the purposeof illustration and example only. Other variations and modifications ofthe present invention will be apparent to those of skill in the art, andit is the intent of the appended claims that such variations andmodifications be covered. The description as set forth is thus notintended to be exhaustive or to limit the scope of the invention. Manymodifications and variations are possible in light of the above teachingwithout departing from scope of the following claims. It is contemplatedthat the use of the present invention can involve components havingdifferent characteristics. It is intended that the scope of the presentinvention be defined by the claims appended hereto, giving fullcognizance to equivalents in all respects.

What is claimed is:
 1. A method for fabricating a capacitor formed on asubstrate wherein said capacitor is utilized in a semiconductor device,said method comprising the steps of: designating a salicide gate for usewith said semiconductor device; configuring a self-aligned contact foruse with said semiconductor device; and combining said salicide gate anda self-aligned contact in a memory cell area of said semiconductordevice to thereby permit the efficient shrinkage of memory cell sizewithout an additional mask or weakening of associated circuitperformance.
 2. The method of claim 1 further comprising the steps of:patterning a poly gate on said substrate with a hard mask; andperforming a cell implant thereof.
 3. The method of claim 2 furthercomprising the step of: depositing TEOS, SiN, BPTEOS on said substrate;and performing an IPO-1 planarization upon a layer formed on saidsubstrate.
 4. The method of claim 3 further comprising the step of:performing an anisotropic etch back thereof to stop on said poly gateutilizing high selectivity between said poly gate and said anisotropicetch back, wherein said anisotropic etch back comprises anisotropic etchback based on a combination of oxide and SiN.
 5. The method of claim 4further comprising the steps of: defining a logic poly gate; performingan LDD implant upon said substrate; and forming a spacer depositionlayer upon said substrate.
 6. The method of claim 5 further comprisingthe steps of: performing a spacer TEOS dry etch followed by a stop atSiN; utilizing an additional photo mask to open an associated DRAMarray; and utilizing a wet dip upon said substrate and said layersthereof to remove a spacer TEOS.
 7. The method of claim 6 furthercomprising the steps of: performing a spacer SiN dry etch upon saidsubstrate and said layers thereof followed by a stop on a TEOS; andutilizing a wet dip upon said substrate and said layers thereof toremove said spacer TEOS.
 8. The method of claim 7 further comprising thestep of: defining an RPO upon said substrate; and forming a Co-salicideupon said substrate for use with said semiconductor device.
 9. Themethod of claim 8 further comprising the step of: utilizing saidcapacitor formed between a metal-one layer and a metal-two layer uponsaid substrate in said semiconductor device, wherein said capacitorcomprises an MIM capacitor.
 10. The method of claim 1 wherein saidsemiconductor device comprises a DRAM-based semiconductor device. 11.The method of claim 2 wherein said poly gate comprises a DRAM poly gate.12. The method of claim 2 wherein said cell implant comprises a cell LDDimplant.
 13. The method of claim 1 wherein said capacitor comprises anMIM capacitor.
 14. A method for fabricating a MIM capacitor upon asubstrate, wherein said MIM capacitor is utilized in a DRAM-basedsemiconductor device thereof, said method comprising the steps of:patterning a DRAM poly gate upon said substrate with a hard mask;performing a cell LDD implant upon said substrate; depositing TEOS, SiN,and BPTEOS layers upon said substrate; forming a IPO-1 planarizationlayer upon said substrate; performing an anisotropic etch back upon saidsubstrate and layers thereof to stop on said poly gate utilizing highselectivity between said poly gate and said anisotropic etch back,wherein said anisotropic etch back comprises anisotropic etch back basedon a combination of oxide and SiN; defining a logic poly gate upon saidsubstrate and layers thereof; performing an LDD implant upon saidsubstrate and layers thereof; performing a spacer deposition upon saidsubstrate and layers thereof; performing a spacer TEOS dry etch followedby a stop at SiN upon said substrate and layers thereof; utilizing anadditional photo mask to open an associated DRAM array; utilizing a wetdip upon said substrate and layers thereof to remove a spacer TEOS;performing a spacer SiN dry etch upon said substrate and layers thereoffollowed by a stop on a TEOS; utilizing a wet dip upon said substrateand layers thereof to remove said spacer TEOS. defining an RPO upon saidsubstrate and layers thereof; and forming a Co-salicide upon saidsubstrate and layers thereof for use with said semiconductor device.utilizing said capacitor between a metal-one layer and a metal-two layerupon said substrate and layers thereof, wherein said capacitor comprisesan MIM capacitor.
 15. A system for fabricating a capacitor formed on asubstrate wherein said capacitor is utilized in a semiconductor device,said system comprising: a salicide gate designated for use with saidsemiconductor device, wherein said salicide gate is formed upon saidsubstrate and layers thereof; a self-aligned contact configured for usewith said semiconductor device, wherein said self-aligned contact isformed upon said substrate and layers thereof; and said salicide gateand said self-aligned contact combined in a memory cell area of saidsemiconductor device upon said substrate and layers thereof to therebypermit the efficient shrinkage of memory cell size without an additionalmask or weakening of associated circuit performance.
 16. The system ofclaim 15 further comprising: a poly gate patterned with a hard mask uponsaid substrate and layers thereof; and a cell implant upon saidsubstrate and layers thereof.
 17. The system of claim 16 furthercomprising: depositions of TEOS, SiN, BPTEOS formed upon said substrateand layers thereof; and an IPO-1 planarized layer thereof.
 18. Thesystem of claim 17 further comprising: an anisotropic etch back thatstops on said poly gate, wherein said anisotropic etch back is performedutilizing high selectivity between said poly gate and said anisotropicetch back, such that said anisotropic etch back comprises anisotropicetch back based on a combination of oxide and SiN.
 19. The system ofclaim 18 further comprising: a logic poly gate defined upon saidsubstrate and layers thereof; an LDD implant; and a spacer depositionlayer formed upon said substrate and layers thereof.
 20. The system ofclaim 19 further comprising: a spacer TEOS dry etch followed by a stopat SiN upon said substrate and layers thereof; a photo mask which may beutilized to open an associated DRAM array; and a wet dip upon saidsubstrate and layers thereof, wherein said wet dip removes said spacerTEOS.
 21. The system of claim 20 further comprising: a spacer SiN dryetch performed upon said substrate and layers thereof followed by a stopon a TEOS; and a wet dip which removes said spacer TEOS performed uponsaid substrate and layers thereof.
 22. The system of claim 21 furthercomprising: an RPO defined upon said substrate and layers thereof; and aleast one Co-salicide formed upon said substrate and layers thereof foruse with said semiconductor device.
 23. The system of claim 22 furthercomprising: said capacitor formed between a metal-one layer and ametal-two layer in said semiconductor device upon said substrate andlayers thereof, wherein said capacitor comprises an MIM capacitor. 24.The system of claim 15 wherein said semiconductor device comprises aDRAM-based semiconductor device.
 25. The system of claim 16 wherein saidpoly gate comprises a DRAM poly gate.
 26. The system of claim 16 whereinsaid cell implant comprises a cell LDD implant.
 27. The system of claim15 wherein said capacitor comprises an MIM capacitor.
 28. A system forfabricating a MIM capacitor utilized in a DRAM-based semiconductordevice, said system comprising: a DRAM poly gate patterned with a hardmask upon said substrate and layers thereof; a cell LDD implant; TEOS,SiN, and BPTEOS deposition layers formed upon said substrate and layersthereof; an IPO-1 planarized layer formed upon said substrate and layersthereof; an anisotropic etch back formed upon said substrate and layersthereof which stops on said poly gate, wherein said anisotropic etchback is performed utilizing high selectivity between said poly gate andsaid anisotropic etch back, such that said anisotropic etch backcomprises an anisotropic etch back based on a combination of oxide andSiN; a logic poly gate defined upon said substrate and layers thereof;an LDD implant; a spacer deposition layer formed upon said substrate andlayers thereof; a spacer TEOS dry etch followed by a stop at SiN uponsaid substrate and layers thereof; a photo mask which opens anassociated DRAM array; a wet dip upon said substrate and layers thereofwhich removes a spacer TEOS; a spacer SiN dry etch performed upon saidsubstrate and layers thereof followed by a stop on a TEOS; a wet dipperformed upon said substrate and layers thereof, wherein said wet dipremoves said spacer TEOS. an RPO defined upon said substrate and layersthereof; a Co-salicide formed for use with said semiconductor deviceupon said substrate and layers thereof. said capacitor formed between ametal-one layer and a metal-two layer upon said substrate and layersthereof, wherein said capacitor comprises an MIM capacitor.